SystemVerilog mode

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 // Literals 1'b0 1'bx 1'bz 16'hDC78 'hdeadbeef 'b0011xxzz 1234 32'd5678 3.4e6 -128.7 // Macro definition `define BUS_WIDTH = 8; // Module definition module block( input clk, input rst_n, input [`BUS_WIDTH-1:0] data_in, output [`BUS_WIDTH-1:0]
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            data_out ); always @(posedge clk or negedge rst_n) begin if (~rst_n) begin data_out
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            <=8 'b0;
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    end else begin
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      data_out <= data_in;
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    end
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    if (~rst_n)
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      data_out <= 8'b0; else data_out <=d ata_in; if (~rst_n) begin data_out <=8 'b0;
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      end
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    else
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      begin
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        data_out <= data_in;
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      end
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  end
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endmodule
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// Class definition
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class test;
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  /**
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   * Sum two integers
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   */
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  function int sum(int a, int b);
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    int result = a + b;
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    string msg = $sformatf("%d + %d = %d", a, b, result);
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    $display(msg);
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    return result;
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  endfunction
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  task delay(int num_cycles);
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    repeat(num_cycles) #1;
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  endtask
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endclass
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