SystemVerilog mode

​x
 
1
 // Literals 1'b0 1'bx 1'bz 16'hDC78 'hdeadbeef 'b0011xxzz 1234 32'd5678 3.4e6 -128.7 // Macro definition `define BUS_WIDTH = 8; // Module definition module block( input clk, input rst_n, input [`BUS_WIDTH-1:0] data_in, output [`BUS_WIDTH-1:0]
2
​
3
            data_out ); always @(posedge clk or negedge rst_n) begin if (~rst_n) begin data_out
4
​
5
            <=8 'b0;
6
​
7
    end else begin
8
​
9
      data_out <= data_in;
10
​
11
    end
12
​
13
14
​
15
    if (~rst_n)
16
​
17
      data_out <= 8'b0; else data_out <=d ata_in; if (~rst_n) begin data_out <=8 'b0;
18
​
19
      end
20
​
21
    else
22
​
23
      begin
24
​
25
        data_out <= data_in;
26
​
27
      end
28
​
29
​
30
​
31
  end
32
​
33
34
​
35
endmodule
36
​
37
​
38
​
39
// Class definition
40
​
41
class test;
42
​
43
​
44
​
45
  /**
46
​
47
   * Sum two integers
48
​
49
   */
50
​
51
  function int sum(int a, int b);
52
​
53
    int result = a + b;
54
​
55
    string msg = $sformatf("%d + %d = %d", a, b, result);
56
​
57
    $display(msg);
58
​
59
    return result;
60
​
61
  endfunction
62
​
63
64
​
65
  task delay(int num_cycles);
66
​
67
    repeat(num_cycles) #1;
68
​
69
  endtask
70
​
71
72
​
73
endclass
74
​
75
​
76
​
77
​

Syntax highlighting and indentation for the Verilog and SystemVerilog languages (IEEE 1800).

Configuration options:

MIME types defined: text/x-verilog and text/x-systemverilog.